1. Field of the Invention
The present invention relates to a reference data recognition learning method of making reference data recognition learning with respect to an associative memory, which compares input pattern search data with several reference data to select and output the most similar data. Further, the present invention relates to a pattern recognition system for carrying out the reference data recognition learning using the foregoing method.
2. Description of the Related Art
In a pattern recognition system, pattern matching is a significant element in a recognition process. A model realized using a processor as a base is the most general in a conventional system. The model employs the method of sequentially comparing input pattern data with several reference data stored in memory to detect the most similar reference data. However, the method employed in the model has the following problems. Sequential comparison is required; for this reason, much processing time is taken. In addition, the processing time increases in proportion to the increase of the number of comparison data. The reference data is sequentially compared; for this reason, no learning concept exists in replacement of comparison sequence and registration of novel reference data. As a result, the effect of shortening the process time by learning is not obtained.
Pattern recognition and learning is a function indispensable to build up an artificial intelligence system having the same capability as the human brain. For this reason, it is technically very important to realize the foregoing function using integrated circuits. A neural network is used in most of the methods proposed so far in order to realize pattern recognition and learning function (for example, see Document 1). However, according to the method of using the neural network, there is no preferable method of effectively storing patterns. For this reason, pattern information must be captured in the network structure. In order to make the network learn to make new pattern recognition after network learning is already completed, relearning is newly required in the whole of the network. Thus, learning while making recognition process is difficult. Recently, the development of the method of realizing recognition function by hardware using the neural network is later than initially expected. For these reasons in the point of view of integration and power dissipation realizing neural a neural network LSI is difficult. For this reason, it is desired to provide a method of realizing the recognition function by excellent and new hardware effectively combining memory elements.
Considering the circumstances described above, the research and development of a compact and high-speed associative memory with fully parallel architecture (e.g., Documents 2 to 7) have been recently made. It is proposed to use the foregoing associative memory for pattern matching. The associative memory has the minimum distance search function, which is a significant element to realize the recognition function. The associative memory is capable of making a comparison between search data and each reference data using analog-digital hybrid and fully parallel processing. Thus, the associative memory has attracted special interest because it is expected to realize high-speed pattern matching.
However, in the pattern recognition system using the foregoing associative memory as a base, an effective learning method of recognizing new reference data is not established. For this reason, considerable time is taken to add or replace the reference data.
Reference Documents:
[Document 1] Iwata and Y. Amemiya, “Neural network LSI”, Denshi Joho Tsuushin Gakkai, 1995.
[Document 2] H. J. Mattausch, et al. “Compact associative-memory architecture with fully-parallel search capability for the minimum Hamming distance”, IEEE Journal of Solid-State Circuits, vol. 37, pp. 218-227, 2002.
[Document 3] H. J. Mattausch, et al. “Fully-parallel pattern-matching engine with dynamic adaptability to Hamming or Manhattan distance”, 2002 Symposiums on VLSI circuit Dig of Tech. Papers, pp. 252-255, 2002.
[Document 4] H. J. Mattausch, et al. “An architecture for compact Associative Memories with Deca-ns Nearest-Match Capability up to Large Distance”, ISSCC Dig of Tech. Papers, pp. 170-171, 2001.
[Document 5] JPN. PAT. APPLN. No. 2002-008783 (JPN. PAT. APPLN. KOAKI Publication No. 2002-288985)
[Document 6] JPN. PAT. APPLN. No. 2002-159436 (JPN. PAT. APPLN. KOAKI Publication No. 2004-005825)
[Document 7] JPN. PAT. APPLN. No. 2002-165769 (JPN. PAT. APPLN. KOAKI Publication No. 2004-013504)